Processors are designed to execute instructions and store results in registers, the results possibly being utilized as operands for subsequent instructions. Parallel processing architectures such as today's graphics processing units (GPUs) include a large number of parallel execution units configured to execute a large number of threads in parallel. The GPUs may also implement pipelined execution units that enable multiple, long-latency operations to be in flight at the same time. Many processors execute instructions in-order relative to the order of the instructions defined by the program. However, some processors allow for out-of-order execution of instructions. Due to the possibility that some instructions may depend on previously executed instructions and that strict ordering of instruction execution may not be adhered to by the processor, processors may be required to implement some form of scheduling mechanism to ensure that register dependencies are managed properly. Thus, there is a need for addressing this issue and/or other issues associated with the prior art.